1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a high voltage integrated circuit with a freewheeling diode embedded in a high voltage transistor.
2. Description of the Related Art
FIGS. 1A and 1B are schematic circuit diagrams of a conventional high voltage integrated circuit 10 for driving a motor, wherein FIG. 1A is a circuit diagram of the circuit 10 in a normal operation mode and FIG. 1B is a circuit diagram of the circuit 10 in a freewheeling operation mode. The motor operates as an inductive load, wherein not only a parasitic operation but also a current sink from another block must be always taken into consideration. The high voltage integrated circuit 10 uses a PWM scheme and includes first through fourth transistors Q11, Q12, Q13 and Q14. For example, the first and fourth transistors Q11 and Q14 contribute to the clockwise rotation of a motor M, while the second and third transistors Q12 and Q13 contribute to the counterclockwise rotation of the motor M. First through fourth diodes DP11, DP12, DP13 and DP14 respectively connected in parallel to the first through fourth transistors Q11, Q12, Q13 and Q14 are parasitic diodes and operate in a freewheeling operation mode.
A first switching device pair configured to include the first and fourth transistors Q11 and Q14 and a second switching device pair configured to include the second and third transistors Q12 and Q13 are selectively turned on to alternately change the direction of a current flowing through the motor M. For example, when the first and fourth transistors Q11 and Q14 are turned on and the second and third transistors Q12 and Q13 are turned off, a current IL1 flows through the first transistor Q11, the motor M and the fourth transistor Q14, as illustrated in FIG. 1A. Accordingly, the motor M normally rotates in a clockwise direction, for example.
Thereafter, when the first and fourth transistors Q11 and Q14 are turned off, the inductive load characteristics of the motor M cause a current IL2 to flow through the second and third diodes DP12 and DP13, as illustrated in FIG. 1B. This is called a freewheeling mode. Accordingly, in the freewheeling mode, the voltage of an output node Vo+ is maintained lower than that of a ground node by about −1V. This lower voltage of the output node Vo+ causes a current sink from another block (e.g., a control block) to the output node Vo+. This current sink causes noise or signal distortion to occur, resulting in malfunction of the control block.
FIG. 2A illustrates a plan view of a conventional high voltage integrated circuit for driving a motor, and FIG. 2B is a sectional view taken along a line IIb-IIb of FIG. 2A. FIGS. 2A and 2B particularly illustrate the third transistor Q13 and the third diode DP13 of FIG. 1A or 1B.
FIGS. 2A and 2B show a device isolation region 103 disposed between a control block 105 and a power block 101. The power block 101 is surrounded by the device isolation region 103 and is thus isolated from the control block 105. An N-type epitaxial layer 120 is formed on a semiconductor layer 100, and an N+-type buried layer 110 is formed between the semiconductor layer 100 and the N-type epitaxial layer 120. A high voltage transistor is formed in the power block 101. The high voltage transistor includes a P-type base region 150 formed in the N-type epitaxial layer 120, an N+-type emitter region 160 formed in the P-type base region 150, and a collector region 130 that is an N+-type sink region.
A parasitic NPN bipolar transistor QP11 is formed of a P-type impurity region 140 formed in the device isolation layer 103, the N+-type sink region 130 of the power block 101, and an N+-type sink region 130a formed in the control block 105. Accordingly, a current sink occurs from the control block 105 through the parasitic NPN bipolar transistor QP11. In order to prevent this current sink, a sufficient distance d1 of, for example, about 300 μm must be maintained between the control block 105 and the power block 101. This causes a device size and a substrate resistance to increase.
In order to prevent the current sink caused by the parasitic transistor QP11, a method using a guard ring formed in the device isolation region has been proposed.
FIG. 3A illustrates a plan view of another conventional high voltage integrated circuit having a guard ring and driving a motor, and FIG. 3B is a sectional view taken along a line of FIG. 3A. FIGS. 3A and 3B particularly illustrate the third transistor Q13 and the third diode DP13 of FIG. 1A or 1B.
FIGS. 3A and 3B show a device isolation region 103 disposed between a power block 101 and a control block 105. The device isolation region 103 includes P-type impurity regions 140 and 145, and an N+-type guard ring 135 formed between the P-type impurity regions 140 and 145. The formation of the N+-type guard ring 135 reduces a current sink from the control block 105 to the power block 101. Parasitic diode DP13 includes N+-type sink region 130 acting as a cathode and substrate 100 acting as an anode.
However, a parasitic NPN transistor QP11 still exists due to an N+-type sink region 130a of the control block 105, the P-type impurity region 140, and an N+-type sink region 130. In addition, a parasitic NPN transistor QP22 is formed of the N+-type sink region 130a of the control block 105, the P-type impurity region 145, and the N+-type sink region 130. Also, a parasitic NPN transistor QP21 is formed of the N+-type guard ring 135 of the device isolation region 103, the P-type impurity region 145, and the N+-type sink region 130. Accordingly, a current sink still occurs from the control block 105 to the power block 101. Also, since the N+-type guard ring 135 must be spaced apart from the control block 105 by at least 300 μm so as to reduce the current sink, the width of the device isolation region 103 increases according to the formation of the N+-type guard ring 135.
In another conventional high voltage integrated circuit, a method using a double guard ring formed in the device isolation region has been proposed.
FIG. 4A illustrates a plan view of another conventional high voltage integrated circuit having the double guard ring and driving a motor, and FIG. 4B is a sectional view taken along a line IVb-IVb of FIG. 4A. FIGS. 4A and 4B particularly illustrate the third transistor Q13 and the third diode DP13 of FIG. 1A or 1B.
FIGS. 4A and 4B show N+-type guard rings 135 and 137 which are formed in a device isolation region 103 between a power block 101 and a control block 105. The formation of the N+-type guard rings 135 and 137 reduces a current sink from the control block 105 to the power block 101. Also, a PN junction is formed of P-type impurity regions 140 and 145 of the device isolation region 103 and parasitic freewheeling diodes DP1′ and DP2′ are formed due to the formed PN junction, which is more advantageous to the freewheeling operation of the motor.
However, also in this method, a parasitic NPN transistor QP11 still exists due to an N+-type sink region 130a of the control block 105, the P-type impurity region 140, and an N+-type sink region 130. In addition, a parasitic NPN transistor QP22 is formed of the N+-type sink region 130a of the control block 105, a P-type impurity region 147 of the device isolation region 103, and the N+-type sink region 130. Also, a parasitic NPN transistor QP21 is formed of the N+-type guard ring 137 of the device isolation region 103, the P-type impurity region 140, and the N+-type sink region 130. Also, a parasitic NPN transistor QP31 is formed of the N+-type sink region 130a of the control block 105, the P-type impurity region 145, and the N+-type sink region 130. Accordingly, a current sink still occurs from the control block 105 to the power block 101. Also, the width of the device isolation region 103 further increases according to the formation of the N+-type guard rings 135 and 137 constituting the double guard ring.